Industrial6 LayersGaN, Power Electronics, High-Density

3.3 kW GaN Bidirectional DC-DC Converter — PCB Design Case Study

6-layer high-power-density bidirectional DC-DC converter using GaN half-bridge modules. Targets 3.3 kW continuous power transfer at 96.2% peak efficiency for on-board EV battery charging and regenerative braking applications.

GaNDC-DCPhase-Shift Full BridgeIsolatedEV ChargingHigh Efficiency

Problem Statement

An e-mobility startup needed a bidirectional isolated DC-DC converter fitting a 120 mm × 80 mm board. The design had to achieve >96% efficiency at 3.3 kW, pass EN 55032 Class B emissions, and tolerate 600 V bus transients. The previous design using Si MOSFETs measured 93.1% efficiency and ran thermally marginal at ambient temperatures above 50 °C.

Design Constraints & Specs

  • 6-layer 2 oz copper stackup — high current paths on outer layers, gate drives on inner layers
  • GaN half-bridge modules switching at 400 kHz — PCB parasitic inductance in commutation loop < 1 nH
  • Phase-shift full-bridge topology with synchronous rectification — 4 independent gate drive channels with <5 ns propagation delay matching
  • Primary bus: 400 V; secondary bus: 48 V. Isolation: 3 kV reinforced (EN 62368-1)
  • Thermal target: GaN junction < 100 °C at 3.3 kW, 70 °C ambient, natural convection
  • PCB size: 120 mm × 80 mm — dictated by enclosure

Design Challenges Solved

  • Minimized GaN commutation loop inductance to 0.7 nH by co-planar placement of half-bridge modules with return current path in adjacent copper layer, eliminating voltage overshoot that was destroying previous Si MOSFET designs
  • Achieved 3 kV isolation using slotted PCB clearance with conformal-coat-filled slots, passing Hi-Pot at 3.6 kV without creepage augmentation components
  • Gate drive Kelvin connections routed on a dedicated inner layer shielded from switching node — eliminated gate ringing that had caused false turn-on in pre-prototype simulations
  • Thermal optimization: embedded copper heat spreader in inner layers beneath GaN modules reduced thermal resistance Rth(j-board) from 4.2 K/W to 1.8 K/W; measured junction temperature 87 °C at full load

Deliverables

  • Schematic with isolated gate drive design and full power stage annotation
  • 6-layer layout with 2 oz copper current path analysis and parasitic extraction results
  • Thermal simulation report (steady-state FEA) with temperature map
  • EN 55032 pre-compliance conducted emissions scan results
  • Fabrication files with impedance and copper weight specifications
  • Assembly drawing with torque specifications for heatsink standoffs

Outcome

Measured efficiency of 96.4% at 3.3 kW, exceeding the 96% target. Thermal measurements confirmed 89 °C junction at 70 °C ambient. EN 55032 Class B conducted emissions passed with 6 dB margin. Client filed provisional patent citing the commutation loop layout topology.

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